As a result of continued improvements in semiconductor materials and wafer processing techniques, integrated circuit topologies are currently capable of being fabricated at submicron line width resolution. Unfortunately, conventional chip-to-package interconnect processing, such as flip chip, beam lead, wire bonding or tape automated bonding (of which wire bonding and TAB are the only practical schemes for high density, high reliability packaging), has not kept pace. Wire bonding systems, for example, customarily require a large pitch (on the order of 5-6 mils between bond sites). TAB processing, on the other hand, requires expensive hard tooling and lengthy preparation cycles to produce the tape, which itself has a practical limit to the pitch of the leads (on the order of 4 mils) that can be economically produced in quantity.